The short answer: the data rate of an HDMI to MIPI DSI conversion is not a fixed number—it depends entirely on the resolution, refresh rate, color depth, and the specific conversion chipset used. For a typical 1080p60 24-bit RGB signal, the MIPI DSI output runs at about 1.5 Gbps per lane over 4 lanes, totaling around 6 Gbps. But that’s just the raw pixel clock. When you factor in blanking intervals, overhead, and protocol differences, the actual effective data rate can vary from 500 Mbps to over 12 Gbps. Let’s break down the numbers and the real-world constraints.
HDMI vs MIPI DSI: the fundamental mismatch
HDMI is a serialized video interface designed for long cables and consumer electronics, with built-in audio, CEC, and HDCP. It uses TMDS (Transition Minimized Differential Signaling) with a fixed 3.3V swing. MIPI DSI, on the other hand, is a low-power, high-speed serial interface meant for short PCB traces inside mobile devices, tablets, and displays. It uses differential signaling at 1.2V or 1.8V, with a flexible number of lanes (1 to 4, sometimes 8). The conversion chip must re-encode the HDMI stream into MIPI DSI packets, which adds latency and overhead.
Raw data rate calculation
For a given resolution, the HDMI pixel clock is: pixel clock = horizontal total × vertical total × refresh rate. For 1920×1080 at 60 Hz with HFP=88, HBP=44, Hsync=44, VFP=4, VBP=2, Vsync=5, the total horizontal is 2200, total vertical is 1125, so pixel clock = 2200×1125×60 = 148.5 MHz. Each pixel at 24-bit color requires 24 bits, so HDMI raw data rate = 148.5 MHz × 24 = 3.564 Gbps. But HDMI uses 8b/10b encoding (TMDS), so the actual line rate is 148.5 MHz × 10 = 1.485 Gbps per TMDS channel, with three channels, totaling 4.455 Gbps.
MIPI DSI uses 8b/9b encoding (or 8b/10b in some older versions), so the effective data rate per lane is: lane rate = pixel clock × bits per pixel / number of lanes. For 1080p60, 24 bpp, 4 lanes, lane rate = 148.5×24/4 = 891 MHz (or 891 Mbps per lane). But MIPI DSI also requires blanking packets and sync packets, so the actual lane rate is typically set to 1.0 Gbps per lane for safety, giving 4 Gbps total. Some chips can run at 1.5 Gbps per lane, allowing 6 Gbps for 4K at 30 Hz.
Real-world conversion chips and their limits
Common chips like the hdmi to mipi dsi display adapter from DisplayModule use the LT8918 or similar. The LT8918 supports up to 4K@30Hz input, which means a pixel clock of 297 MHz for 3840×2160@30. For 24-bit color, that’s 297×24 = 7.128 Gbps raw. With 4 MIPI lanes at 1.5 Gbps each, total is 6 Gbps—so the chip must compress or reduce color depth. Many adapters drop to 18-bit (6 bits per channel) for 4K, reducing the data rate to 297×18 = 5.346 Gbps, which fits within 4 lanes at 1.5 Gbps. For 1080p60, 24-bit, 4 lanes at 1.0 Gbps is standard.
Here’s a table of common configurations:
| Resolution | Refresh | Color Depth | Pixel Clock (MHz) | Raw Data Rate (Gbps) | MIPI Lanes | Lane Rate (Gbps) | Total MIPI BW (Gbps) |
|---|---|---|---|---|---|---|---|
| 1920×1080 | 60 Hz | 24-bit | 148.5 | 3.564 | 4 | 1.0 | 4.0 |
| 1920×1080 | 60 Hz | 18-bit | 148.5 | 2.673 | 4 | 0.7 | 2.8 |
| 3840×2160 | 30 Hz | 24-bit | 297 | 7.128 | 4 | 1.5 | 6.0 |
| 3840×2160 | 30 Hz | 18-bit | 297 | 5.346 | 4 | 1.5 | 6.0 |
| 1024×600 | 60 Hz | 24-bit | 51.2 | 1.229 | 2 | 0.6 | 1.2 |
Note that the lane rate is often set to a standard value like 1.0 Gbps, 1.2 Gbps, or 1.5 Gbps, not the exact calculated number. The chip’s PLL generates the clock based on the input pixel clock and the number of lanes. For example, with a 148.5 MHz pixel clock and 4 lanes, the ideal lane rate is 148.5×24/4 = 891 MHz, but many chips round up to 1.0 Gbps to simplify timing.
Overhead and blanking
MIPI DSI uses packet-based transmission, not continuous streaming like HDMI. Each horizontal line is transmitted as a burst of packets, followed by blanking intervals. The blanking period in MIPI DSI is not fixed—it’s determined by the chip’s configuration. If the blanking is too short, the display might show artifacts. Most adapters preserve the HDMI blanking ratios, but some chips can compress the blanking to reduce the data rate. For instance, reducing horizontal blanking from 280 pixels to 160 pixels for 1080p60 drops the pixel clock to 1920×1080×60 = 124.4 MHz, reducing the data rate by 16%. But this can cause compatibility issues with displays that expect specific timing.
The conversion also adds a latency of 1-2 scanlines (about 15-30 microseconds at 1080p60), which is negligible for most applications but can be critical for real-time video processing. The chip must buffer the incoming HDMI stream in a FIFO and re-pack it into MIPI packets. This buffer size is typically 4-8 KB, which limits the maximum resolution and refresh rate.
Impact of color depth and compression
Many HDMI to MIPI DSI adapters support 24-bit RGB (8 bits per channel) but fall back to 18-bit (6 bits per channel) for higher resolutions. Some chips also support 30-bit (10 bits per channel) for HDR, but that requires 5 Gbps per lane, which is rare. For example, a 4K@60Hz 24-bit signal requires 594 MHz pixel clock and 14.256 Gbps raw data rate. With 4 MIPI lanes, that’s 3.564 Gbps per lane—beyond the MIPI DSI spec (max 1.5 Gbps per lane for D-PHY, 2.5 Gbps for D-PHY v2.0). So 4K@60Hz is not possible with standard DSI; you’d need 8 lanes at 1.5 Gbps or 4 lanes at 3.5 Gbps, which is not common in consumer adapters. That’s why most HDMI to MIPI DSI boards cap at 4K@30Hz or 1080p@60Hz.
Some chips use DSC (Display Stream Compression) to reduce the data rate. For example, DSC at 3:1 compression can turn a 4K@60Hz 24-bit signal into 4.752 Gbps, which fits in 4 lanes at 1.2 Gbps. But DSC is not universally supported in MIPI DSI displays, and it adds latency and complexity. Most low-cost adapters don’t include DSC.
Real-world performance of the LT8918 chip
The LT8918 is a popular chip for HDMI to MIPI DSI conversion. Its datasheet specifies a maximum pixel clock of 297 MHz (4K@30Hz), a maximum MIPI lane rate of 1.5 Gbps, and support for 1-4 lanes. For 1080p60, it uses 4 lanes at 1.0 Gbps, giving a total bandwidth of 4 Gbps, which is enough for 3.564 Gbps raw data. The chip also supports audio embedding (I2S or SPDIF) into the MIPI stream, which adds about 1-2 Mbps of overhead. The power consumption is around 200-300 mW, depending on the resolution.
Another common chip is the TC358870XBG, which supports up to 4K@30Hz and 4 lanes at 1.2 Gbps. It has a built-in scaler that can downscale 4K to 1080p for displays that can’t handle 4K. The data rate in that case is the same as 1080p60, but the chip adds a 1-frame latency (16.7 ms at 60 Hz) due to the scaling buffer.
For lower resolutions like 1024×600, the data rate drops significantly. With a pixel clock of 51.2 MHz and 24-bit color, raw data is 1.229 Gbps. Using 2 lanes at 0.6 Gbps each gives 1.2 Gbps total, which is just enough. Many adapters use 2 lanes for lower resolutions to save power and reduce chip complexity.
Cable and signal integrity
The physical connection between the HDMI source and the adapter board also affects the achievable data rate. HDMI cables are rated for specific bandwidths: Category 1 (Standard) supports up to 2.25 Gbps (720p/1080i), Category 2 (High Speed) supports up to 10.2 Gbps (1080p/4K@30), and Category 3 (Ultra High Speed) supports up to 48 Gbps (4K@120/8K@60). If you use a cheap 5-meter cable with a 4K@30Hz signal, the signal degradation can cause the adapter to drop to 1080p or 18-bit color. The MIPI DSI output is also sensitive to PCB trace length and impedance. Most adapter boards use 50-ohm traces and keep the MIPI traces under 10 cm to avoid signal loss. The lane rate of 1.5 Gbps corresponds to a signal frequency of 750 MHz (since DDR), which requires careful PCB design.
Temperature also affects the data rate. The LT8918 has a maximum operating temperature of 85°C. At 70°C, the PLL might drift, causing timing errors. Many adapters include a heatsink for 4K operation. The power supply must provide clean 3.3V and 1.8V rails; noise on the power lines can cause bit errors on the MIPI lanes, forcing the chip to reduce the lane rate.
Comparison with other interfaces
For context, LVDS (Low-Voltage Differential Signaling) is an older interface used in many laptop panels. A single LVDS link at 85 MHz pixel clock supports 1366×768@60 with 24-bit color. Dual LVDS links can do 1920×1080@60. The data rate for a single LVDS link is about 1.6 Gbps (4 data pairs at 400 Mbps each). HDMI to LVDS converters are common but have lower bandwidth than MIPI DSI. eDP (Embedded DisplayPort) is another alternative, supporting up to 8.1 Gbps per lane with 4 lanes (32.4 Gbps total). But eDP is not as common in small displays as MIPI DSI. The choice of interface depends on the display’s native input. For a 5-inch 800×480 display, MIPI DSI is the standard because it uses fewer pins and lower power.
Some industrial displays use parallel RGB interfaces, which require 24 data lines plus clocks. HDMI to parallel RGB converters are simpler but have lower data rates (typically 100 MHz pixel clock max, or 2.4 Gbps for 24-bit). MIPI DSI is more efficient for high resolutions because it serializes the data.
Practical considerations for your project
If you’re connecting a 10.1-inch 1280×800 display via MIPI DSI, the pixel clock is about 71 MHz (with blanking), raw data rate is 1.704 Gbps. A 2-lane MIPI DSI at 1.0 Gbps per lane gives 2.0 Gbps, which is enough. But if the display requires 4 lanes, you need a adapter that supports 4 lanes. The hdmi to mipi dsi display adapter from DisplayModule supports 4 lanes and can handle up to 4K@30Hz, so it’s overkill for 1280×800 but gives you headroom. The data rate will be set by the chip’s firmware, which often auto-detects the display’s EDID and adjusts the lane rate. You can also manually set the lane rate via I2C commands in some chips.
For a 720p (1280×720) display at 60 Hz, pixel clock is about 74.25 MHz, raw data rate is 1.782 Gbps. With 2 lanes at 1.0 Gbps, total is 2.0 Gbps, so it works. But if you’re using a 4-lane adapter, the chip will use 2 lanes and leave the other two floating. The power consumption drops by about 30% compared to 4-lane operation.
One common mistake is assuming that the HDMI source’s output data rate is the same as the MIPI DSI input data rate. The conversion chip often re-clocks the signal, so the MIPI DSI lane rate can be different from the HDMI TMDS rate. For example, a 1080p60 HDMI signal has a TMDS clock of 148.5 MHz, but the MIPI DSI lane rate is 1.0 Gbps, which is not a multiple of 148.5. The chip’s PLL generates the MIPI clock from the pixel clock using a fractional divider. This can cause jitter if the PLL is not well-designed. Good chips have a jitter of less than 0.1 UI (unit interval) at 1.0 Gbps.
Finally, the data rate also affects the display’s refresh rate. If the MIPI DSI lane rate is too low, the display might not be able to achieve the full refresh rate. For example, a 1080p60 display requires a minimum lane rate of about 891 Mbps per lane with 4 lanes. If the adapter only supports 1.0 Gbps per lane but the cable introduces loss, the effective lane rate might drop to 900 Mbps, causing flickering or missing pixels. Always check the adapter’s specification for the maximum lane rate and the number of lanes.